Multiple cluster signal processor architecture
US5392446A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Feb 11, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal processor architecture that comprises a data network having multiple ports, a control bus, and a plurality of signal processing clusters connected to at least two ports and the control bus. Each signal processing cluster comprises a system control processor connected to the control bus, a second control bus, and a global bulk memory having multiple ports. A plurality of functional processing elements are connected to the system control processor by way of the second control bus, and each are connected to a port of the global bulk memory. The global bulk memory comprises a subdata flow network having multiple gateways and full crossbar interconnectivity between each of the multiple gateways. The data network and subdata flow network allow data to be transferred between functional processing elements in the signal processing cluster and any functional processing element and global bulk memory in another signal processing cluster, and allow data to be transferred from any functional processing element into and out of the processor architecture. The first control bus is arbitrated for access on a message by message basis and the data network is arbitrated on a message by messa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.