Pulse width modulation circuit apparatus
US5394022A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1992 |
| Grant date | Feb 28, 1995 |
| Priority date | — |
| Expiry date | Dec 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/822
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulse width modulation circuit apparatus comprises delay gates, delay circuits and an A/D converter. The delay gates are connected in cascade fashion and delay an input clock signal by the same delay time with each delay gate. The delay circuits are furnished interposingly between the delay gates and derive as their common output the delayed clock signal from the delay gates. Because the number of delay gates through which the input clock signal passes is proportional to the delay time acquired, these components constitute a delay circuit arrangement that offers high levels of linearity. With the delay circuit arrangement in use, any one of the delay circuits constituting part of that arrangement is supplied selectively with an operating current as per the digital output from the A/D converter. This provides a delayed clock signal whose delay time matches the level of the input analog signal. Thus there is generated a pulse signal whose pulse width corresponds to the period from the time the input clock signal is given until the delayed clock signal is acquired. This pulse signal has a pulse width of excellent linearity corresponding to the level of the input analog signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.