High voltage charge pump and related circuitry
US5394027A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 1993 |
| Grant date | Feb 28, 1995 |
| Priority date | — |
| Expiry date | Nov 1, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Charge pump and related circuitry (30) for operation at low power supply voltages includes voltage elevating circuitry (51), clock voltage level shifting circuitry (53), clock separator (55) and charge pump (57). The voltage elevating circuitry (51) receives a power supply voltage VDD and provides an elevated intermediate output voltage V1. The clock voltage level shifting circuitry (53) receives an input clock signal and the voltage V1. The clock voltage level shifting circuitry (53) shifts the maximum voltage level of the CLOCK1 signal from VDD to V1 and provides this signal, labeled SHIFTED CLOCK, as an output. Clock separator (55) receives the SHIFTED CLOCK signal and provides non-overlapping, elevated clocks CLOCKA, CLOCKB, CLOCKC, and CLOCKD, each having a maximum voltage level of V1. Charge pump 57 utilizes the elevated clock signals to provide a high voltage output VOUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.