Field programmable gate array
US5394103A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1994 |
| Grant date | Feb 28, 1995 |
| Priority date | — |
| Expiry date | Feb 24, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.