Synchronizing signal front end processor for video monitor
US5394171A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1992 |
| Grant date | Feb 28, 1995 |
| Priority date | — |
| Expiry date | Nov 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G1/167
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A synchronizing signal front end processor for video monitors includes a synchronizing signal subprocessor which responds to computer generated horizontal and vertical rate scan signals to provide alternative scan signal coupling in the event of interruption or abnormalities of the applied scan signals. The processor also includes horizontal and vertical synchronizing signal subprocessors which produce output signals indicative of the polarity and frequency of the applied selected scan synchronizing signals. In addition, the vertical and horizontal sync subprocessors provide respective sync out of range signals during sync interruption or abnormality which are utilized to stabilize the monitor display scanning process while switching to alternative scan synchronizing signal sources. The horizontal and vertical sync subprocessors each utilize a counter controlled by an edge detection system to accumulate clock signal count numbers indicative of the positive and negative portions of the applied scan synchronizing signals. These counts are utilized for polarity decoding and frequency decoding within the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.