Single transistor flash electrically programmable memory cell in which a negative voltage is applied to the nonselected word line
US5396459A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 1993 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Feb 16, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory using a single floating gate transistor, wherein a control gate elecrrode is negatively biased while a source region is positively biased, and a writing operation is performed bit by bit by transferring electrons from the floating gate into the source region through Fowler-Nordheim tunneling. And an erasing operation is performed by injecting channel hot electrons from the drain region into the floating gate, or by injecting electrons from a substrate into the floating gate through Fowler-Nordheim tunneling. The source region is connected to an individual bit line, and the drain region to a common line so that over-erasing is averted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.