Programmable error-checking matrix for digital communication system
US5396505A · kind A · utility
6Cited by
14References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1993 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Jul 6, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable system for checking for protocol errors in a communication system includes a matrix for generating error checking signals selected by data fields utilized to implement a communication. If the configuration or protocol is changed the system facilitates reprogramming to compensate for the change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.