Microprocessor system having a single, common internal bus transferring data and instructions in different states of a machine cycle
US5396601A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1993 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Apr 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU core includes an internal resource made up of various kinds of registers, and a controller having a bus control circuit which controls the input and output of data and others among various kinds of buses. A terminal group has a plurality of terminals for interconnecting the CPU core to a peripheral circuit and an external memory. The buses comprise an internal bus to which individual circuits incorporated in the CPU core are interconnected, a data bus interconnected between the CPU core and the external memory for allowing data to be inputted and outputted between the CPU core and the external memory, and a peripheral data bus inerconnected between the CPU core and the peripheral circuit for allowing data to be inputted and outputted between the CPU core and the peripheral circuit. The input and output terminals of all of the circuit portions which constitute the internal resource are interconnected to the internal bus. The bus control circuit has input and output terminals interconnected to the internal bus, data bus, and peripheral data bus for controlling the input and output of data and others among the buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.