Method for making vertical MOS having a deep source region near the channel
US5397728A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1994 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Mar 17, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
A semiconductor device includes a first region, a well-shaped second region formed in the first region and a third region formed in the well-shaped second region, both the first region and the third region have a first conductive type, the well-shaped second region has a second conductive type. A gate electrode is formed on a channel of the well-shaped second region. The channel is sandwiched between the first region and the third region. According to the present invention, the depth of the third region is very deep in a portion near the channel and is very shallow in a portion far from the channel. A resistance of the well-shaped second region near a portion of the third region far from the channel is lower than near the portion of the third region near the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.