Transistor microstructure
US5397904A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1992 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Jul 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
Abstract
A method for isolating transistors and a microstructure for providing isolation for transistors includes a beam located on a substrate. The beam is formed from the same material as the substrate, preferably single crystal silicon, and is released so as to be suspended in the cavity and spaced apart from the substrate. The beam is supported in the cavity by a cantilever structure or by spaced pedestals, or both. One or more transistors are fabricated in the beam, and are thus isolated from the substrate and may be isolated from each other if desired. Contact beams may also be provided to contact the transistor electrodes for interconnection of adjacent transistors or connection of the transistors to electrical circuitry on the substrate. The contact beams also provide mechanical support for the beams. Multiple beams in side-by-side arrays or stacked arrays may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.