Voltage multiplier
US5397931A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 1994 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Jun 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6872
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a voltage multiplier for generating an output voltage which is several times greater than the operating voltage for connection of a load connected to ground to the operating voltage by means of an N-channel power MOS transistor, comprising a plurality of capacitors (C1, C2, C3), a control input (C) for supplying a control signal, an output (V.sub.out), an operating voltage terminal (Vb) and a ground terminal (M). In known voltage multipliers, for rectification and multiplication of the output voltage diodes are used which reduce the maximum output voltage obtainable and restrict the clock frequency of the control signal to a few hundred kHz. In contrast, the voltage multiplier according to the invention has a high efficiency and can also be used at high clock frequencies; it includes a switchover means which comprises a control signal generator (S) having a plurality of inverters (I0, I1, I2, I3) and a first and second group of switch elements which are constructed as MOS field-effect transistors and can be driven with clock frequencies of up to 4 MHz. These MOS field-effect transistors are controlled by means of the control signal generator (S) by …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.