Simple and high speed BICMOS tristate buffer circuit
US5398000A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1994 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Mar 30, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A simple and high speed BiCMOS tristate buffer circuit includes a first transistor coupled to a power supply and a first node. The first transistor has a control terminal coupled to receive a first signal. A second transistor is coupled to the first node and ground. The second transistor has a control terminal coupled to receive a second signal. A first bipolar transistor has a base coupled to the first node, a collector coupled to the power supply, and an emitter coupled to an output node of the circuit. A third transistor is coupled to the output node and the ground. The third transistor has a control terminal coupled to receive the second signal. A switching circuit is coupled to the first node and the output node for connecting the first node to the output node when the first and second signals turn off the first, second, and third transistors such that the output node assumes an open circuit condition. The switching circuit is controlled by a third signal. The first, second, and third signals control the first and second transistors and the switching circuit to provide a path from the first input signal to the output node containing only one inverter, one P-channel transistor,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.