Semiconductor memory device
US5398212A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1994 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Mar 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to the present invention includes: a memory cell array including (2.sup.n +m) memory cells, wherein n and m are integers satisfying the relationship 2.sup.n <2.sup.n +m<2.sup.n+1 ; an address decoder for receiving an address signal of (n+l) bits and for specifying one of the (2.sup.n +m) memory cells in accordance with the address signal; an output circuit for outputting data stored in the memory cell specified by the decoding means; an empty address detecting circuit for receiving at least two bits of the address signal of (n+1) bits and for generating a detection signal which indicates whether the address signal represents an empty address or not; and a control circuit for receiving an enable signal and for generating a control signal for outputting the data stored in the specified memory cell in accordance with the enable signal, wherein the control circuit further receives the detection signal and generates a control signal for inhibiting the data from being output when the address signal specifies an empty address, regardless of the state of the enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.