Method and apparatus for reduced latency in hold bus cycles
US5398244A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1993 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Jul 16, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An innovative protocol and system for implementing the same enables quick release of the bus by the master device, such as a CPU, to permit slave devices access to the bus. In one embodiment, the arbiter can select between the original hold protocol and quick hold protocol according to predetermined criteria which indicates that a low latency response is requested. Upon assertion of a QHOLD signal, the CPU issues a burst last signal to prematurely terminate outstanding burst transactions on the bus in a manner transparent to the slave devices. Once the outstanding bus cycles are complete, the CPU performs an internal backoff to immediately release the bus for access by the slave device requesting access. Any pending burst cycles which were terminated prematurely by the QHOLD signal, are subsequently restarted for the data not transacted by the CPU after the slave device completes access to the bus. The internal backoff mechanism is similarly transparent to the slave devices and does not cause a backoff signal to be issued to the peripherals or devices coupled to the bus. Thus, the addition of a quick hold protocol is added without significant modification of the slave devices' bus …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.