Computer subsystem reset by address dependent RC discharge
US5398265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 1994 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | May 16, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system wherein a system master (11) communicates with a plurality of subsystems (13, 25, 27, 29), each subsystem (13, 25, 27, 29) is associated with a unique reset address and a reset circuit which recognizes that reset address and generates a reset signal. Each reset circuit includes an address decoder (15) for decoding the reset address to produce a signal which closes a logic gate switch (19). The logic gate switch (19) is repeatedly closed in response to repeated assertions of the address to successively discharge the voltage on a capacitor (C). When the capacitor voltage is discharged to a selected level, a buffer level detector circuit (23) generates the reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.