Number theory mapping generator for addressing matrix structures
US5398322A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 1993 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | May 18, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The generation of number theory mappings and their application to the addressing of matrix structures through the provision of an address generator which is optimized for the general task of applying "on-the-fly" number theory mappings to matrix operands as they are fetched from memory. The address generator comprises a set of six matrix descriptor storage registers, a finite state machine controller, a first decrementer for cyclically decrementing a first matrix size descriptors from a first of the six storage registers, a second decrementer for cyclically decrementing a second matrix size descriptor from a second of the six storage registers, a finite difference engine which adds one of two matrix difference descriptors to a previously calculated address value obtained from an address register, a modulo arithmetic computation unit which computes the residue of the output of the finite difference engine modulo a matrix modulo descriptor, and an adder which adds an offset value stored as a matrix base descriptor to the output of the modulo arithmetic computation unit. The output sequence from the adder is the desired address generator output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.