Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level
US5399890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1994 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Jun 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.