Multi-chip semiconductor arrangements using flip chip dies
US5399898A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1992 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Nov 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multi-chip, multi-tier semiconductor arrangements based upon single and double-sided flip-chips are described. The double-sided flip chips provide raised bump contact means on both major surfaces of a die and provided connections to internal signals within the die, feed through connections between contacts on opposite sides of the die, and jumpered connections between contacts on the same side of the die. Various multi-chip configurations are described. Certain of these flip-chip configuration dramatically increase the ratio of I/O area (periphery) to footprint area, permitting larger numbers of I/O points within a given assembly footprint than would otherwise be possible in a single die configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.