Gate-drive circuit
US5399913A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1992 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Sep 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/61
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate-drive circuit (10) is an interface between a clock (12) and control circuit (14) and a circuit (16) comprising an isolated gate bipolar transistor (IGBT) devices. The clock (12) provides two complementary clock signals (CLK1, CLK2) to the gate-drive circuit (10); the control circuit provides a signal (ENABLE) for turning the gate-drive circuit on and off, and the gate-drive circuit outputs isolated supply voltages (+RAIL, -RAIL), a drive signal (GATE), and a common reference signal (EMITTER). The control signal is sent across an isolation boundary via a 2-MHz push-pull converter in the gate-drive circuit (10). A transformer (T1) in the gate-drive circuit provides the isolation boundary. The power required to switch the IGBT device (16) is sent through the same 2-MHz converter. The secondary of the 2-MHz push-pull transformer (T1) is referenced to the IGBT emitter. As the primary side circuitry receives "on" signals from the control board (14), the converter runs and charges secondary-side bulk storage capacitors (C16, C18) in the gate-drive circuit. The gate voltage of the IGBT device is held off until the bulk storage capacitors are charged to a minimum value. When the capa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.