Multi-series inverter arrangement
US5400242A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1993 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Feb 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0824
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a multi-series inverter arrangement comprising a DC circuit including a neutral point output terminal and a multi-series inverter including three series connections of first through fourth GTOs, each connected in parallel with the DC circuit, the juncture of the first and second GTOs and the juncture of the third and fourth GTOs being connected to the neutral point output terminal via respective clamping diodes and the first and third GTOs and the second and fourth GTOs being on and off controlled each other in a conjugate relationship, individual gate driving circuits for the second and third GTOs being designed to provide a larger gate current, in particular, a larger wide width gate forward current to the corresponding GTOs than that provided by individual gate driving circuits for the first and fourth GTOs to the corresponding GTOs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.