Detector circuit for testing semiconductor memory device
US5400282A · kind A · utility
12Cited by
6References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1992 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Jul 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a normal mode of reading and writing data from and to a selected memory cell of a memory cell array. The semiconductor memory device is characterized by control means for switching the normal operation mode to a test mode in response to a test mode signal applied to a certain input terminal, selecting all desired memory cells of the memory cell array at a time, and allowing data applied to a data input terminal to be written to all the selected and desired memory cells at one time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.