Method of metal silicide formation in integrated circuit devices
US5401677A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1993 |
| Grant date | Mar 28, 1995 |
| Priority date | — |
| Expiry date | Dec 23, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/906
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
An improved process for the formation of high quality, high yield platinum silicides on silicon wafers uses a post sputter platinum deposition and high vacuum bake to complete the first step of silicide reaction, resulting in Pt.sub.2 Si formation before sinter. This additional process step is then followed by a 500.degree. to 900.degree. C. sinter. The use of a high vacuum bake provides easy control of O.sub.2 and H.sub.2 O impurities. The vacuum bake can be done in any high vacuum tool. The bake temperatures range from 200.degree. to 450.degree. C. at 5.times.10.sup.-6 torr, with an in-situ bake time of 3 to 5 minutes or an ex-situ bake time of 10 to 30 minutes, depending on batch size or tool. A particular advantage of the process is that it can be performed in existing tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.