Self-cascoding CMOS device
US5401987A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1993 |
| Grant date | Mar 28, 1995 |
| Priority date | — |
| Expiry date | Dec 1, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A self-cascoding transconductance circuit has cascoding and current sink/source FETs, serially connected with their gates tied together to receive an input voltage, wherein the cascoding FET has a threshold voltage having an absolute value at least 0.1 volts less than that of the current sink/source FET to ensure that the current sink/source FET operates in its saturated region. A CMOS structure implementing the self-cascoding transconductance circuit has two doped threshold adjust regions formed beneath a gate electrode such that the two doped threshold adjust regions respectively effectuate the cascode and current sink/source FETs which then share the gate electrode. A method of forming the CMOS structure includes forming two self-cascoding transconductance circuits electrically connected in parallel such that they share a common drain region between their respective gate electrodes, and each has one source region. By forming the two self-cascoding transconductance circuits in such a fashion, the effect of alignment errors contributed by each of the parallel connected self-cascoding transconductance circuits is cancelled out for the combined circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.