Method for fabricating a semiconductor memory device having stacked capacitors
US5403766A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1994 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jul 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A semiconductor memory device having stacked-capacitor type memory cells, each of which contains an MOS transistor and a storage capacitor. The capacitor has a first opposed electrode having a recess at its upper face, which is formed through an inter-layer insulation film on the substrate, a first insulation film which covers a surface of the first opposed electrode, a charge storage electrode formed in the recess of the first opposed electrode and contacted with the source region of the transistor through a contact hole of the inter-layer insulation film, a second insulation film which covers a surface of the charge storage electrode, and a second opposed electrode formed on the second insulation film. The charge storage electrodes do not broken in the fabrication sequence of the device. Even if the charge storage electrodes are sheered off in positioning to the corresponding contact holes, the inter-layer insulation film is disadvantageously etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.