Flat semiconductor wiring layers
US5404046A · kind A · utility
30Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1994 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jun 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor circuit device is provided with a first wiring layer connected to a semiconductor substrate through a contact hole in an insulation film formed on a main surface of the semiconductor substrate, and a second wiring layer connected with the first wiring layer through a through-hole in an interlayer insulation film formed on the first wiring layer, wherein the first wiring is substantially flat on the contact hole and the area of the through-hole is smaller than that of the contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.