Scanning circuit
US5404151A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1992 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jul 28, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3674
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scanning circuit according to the invention has a form of integrated thin film transistors on a substrate, comprising a multiplicity of serially interconnected stages of pass transistors or clocked inverters for successive transmission of a signal with a predetermined delay. Each stage includes only one pass transistor or clocked inverter which is operated by a pair of mutually inverted clock puls. Each stage also comprises an output buffer circuit for providing a scanning signal having a frequency twice as large as said clock pulses by receiving the output of the corresponding pass transistor or clocked inverter via an NOR gate which is operated by one of tile paired clock pulses. The scanning circuit is thus capable of doubly fast scanning of a display, e.g. a high resolution display. The scanning circuit is simple in structure, so that it occupies only a small area on a substrate and gives high yield and reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.