Word line boosting circuit and control circuit therefor in a semiconductor integrated circuit
US5404330A · kind A · utility
61Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1993 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Dec 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A word line boosting circuit and a control circuit therefor in a semiconductor integrated circuit are included. A word line boosting control circuit is connected to receive block select information selecting a first or second memory cell array block synchronized to a predetermined row address, and selectively generates first and second word line voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.