Apparatus for and a method of detecting a malfunction of a FIFO memory
US5404332A · kind A · utility
35Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 1994 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | May 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write address counter for designating a write address of a memory counts up a control counter with an address change. A read address counter for designating a read address of the memory counts down the control counter with the address change. Inputted to an error detecting circuit are a write address counter value, a read address counter value and a control count value. There is detected whether a relationship such as Write Address Count Value-Read Address Count Value=Control Count Value is established or not. If not established, this implies an error, and a reset circuit resets each counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.