Synchronous type semiconductor memory device operating in synchronization with an external clock signal
US5404338A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 31, 1994 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jan 31, 2014 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.