Arbiter with a uniformly partitioned architecture
US5404540A · kind A · utility
5Cited by
16References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1993 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Aug 16, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple-input arbiter first mutually correlates groups of input signals for identifying a particular group, which includes at least one input signal that is a candidate for gaining the overall priority. Thereupon the priority winner is determined in that particular group. Such a hierarchical processing lends itself to an architecture wherein the processing in groups is implemented by cascaded levels of uniform logic blocks. The decomposition in uniform logic blocks considerably simplifies the design of arbiters that process large numbers of input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.