Data processor with plural instruction execution parts for synchronized parallel processing and exception handling
US5404557A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1992 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Nov 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor with plural instruction execution parts for synchronized parallel processing which generates first information indicating the order of each group of instructions having successive instruction addresses and second information indicating the order of each instruction in each group of instructions, which feeds both information to any one of instruction execution parts so that such information is added to respective corresponding instructions. The address control part holds the address of a first instruction of each group of instructions so that an instruction address to be saved can be derived when an exception occurs. Only a first instruction of a first group of instructions is allowed to complete its execution in the instruction execution parts. The first information is updated together with the second information every time the execution of one instruction is completed. The supply of next instructions is brought to a stop on the detection of the occurrence of an exception. Each instruction execution part invalidates, at the time that the executions of all instructions fed earlier than an instruction that has detected the occurrence is complete, the processing of re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.