Microprocessor having external control store
US5404560A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1993 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jun 25, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit (CPU) 10 comprises an external control memory for storing microinstructions which correspond to macroinstructions read from a system memory. The microinstructions are 56 bits in length and are read in 28-bit segments. CPU 10 also comprises an internal memory management unit (MMU) 18 which comprises a plurality of address translation entry (ATE) registers four of which are permanent and sixteen of which are temporary in that the storage of a new translation entry occurs in a least recently used temporary translation entry register. CPU 10 also comprises a plurality of status register bits, some of which are settable only by predefined microinstructions. All of the status register bits are branchable. CPU 10 further comprises a condition code register the state of which may be determined by input signal pins. CPU 10 also comprises address generation logic which may generate a 24, 31 or 32 bit address upon a 32-bit address bus. The address generation logic is further operable for generating a memory storage address; the data being supplied by external logic, such as a coprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.