Method of forming a semiconductor structure having MOS, bipolar, and varactor devices
US5405790A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1993 |
| Grant date | Apr 11, 1995 |
| Priority date | — |
| Expiry date | Nov 23, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/009
Abstract
A varactor (10, 115, 122) is formed using a BICMOS process flow. An N well (28) of a varactor region (13) is formed in an epitaxial layer (22) by doping the epitaxial layer (22) with an N type dopant. A cathode region (55, 132) is formed in the N well (28) by further doping the N well (28) with the N type dopant. Cathode electrodes (91, 114) are formed by patterning a layer of polysilicon (62, 86) over the epitaxial layer (22). Subsequently, the cathode electrodes (91, 114) are doped with an N type dopant. A region adjacent the cathode region (55, 132) is doped to form a lightly doped region (103, 117). The lightly doped region (103, 117) is doped with a P type dopant to form an anode region (109, 119).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.