Semiconductor memory device with stacked capacitor above bit lines
US5406103A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 1994 |
| Grant date | Apr 11, 1995 |
| Priority date | — |
| Expiry date | Jan 26, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
After a word line is formed on a semiconductor substrate, a side-wall insulating film is formed on the side faces of the word line. Subsequently, a first insulating film is deposited thereon. The resulting first insulating film is formed with an opening for a bit line, through which a bit line having an on-bit-line insulating film on its top surface is formed. Thereafter, a second insulating film is deposited thereon. An opening for a charge-storage electrode is then formed in the first and second insulating film by removing, by a specified thickness, the portions of the first insulating film, on-bit-line insulating film, and second insulating film lying in a memory cell array region, followed by the deposition of a charge-storage electrode through the opening for a charge-storage electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.