Multiprocessor cache examiner and coherency checker
US5406504A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1993 |
| Grant date | Apr 11, 1995 |
| Priority date | — |
| Expiry date | Jun 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangement includes a plurality of processes configured to acquire information from selected block entries of the caches. The information is then compared with an array of predetermined valid cache states contained in a state table to detect invalid cache states. A cache examining protocol defines the operational procedures followed by the processes when acquiring and examining the information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.