Apparatus, systems and methods for addressing electronic memories
US5406607A · kind A · utility
14Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1994 |
| Grant date | Apr 11, 1995 |
| Priority date | — |
| Expiry date | Feb 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is disclosed for reducing the number of signal lines passing through a connector (205) comprised of a shift register coupled to a plurality of input data lines and half as many output data lines. When a load signal is received, the shift register latches the data from the input data lines and immediately transmits half of the data to the output data lines and through the connector. When the shift register receives a shift signal, the other half of the data is shifted onto the same output lines and pass through the connector to achieve a two-to-one multiplexing function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.