Patent · US Expired

Tamperproof arrangement for an integrated circuit device

US5406630A · kind A · utility

226Cited by

3References

2Claims

0Family size

Assignee

Motorola, Inc. · US

Inventors

Gerald V. Piosenka · Scottsdale, US
David M. Harrison · Mesa, US
Ronald V. Chandos · Tempe, US

Key dates

Filing date	Jan 10, 1994
Grant date	Apr 11, 1995
Priority date	—
Expiry date	Jan 10, 2014

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3025
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A tamperproof arrangement for an integrated circuit device. The arrangement includes a package and lid fabricated of heavy metals to prevent X-radiation or infrared detection of circuit operation. Sensors and control circuitry are located on the integrated circuit die itself which detect increased temperature and radiation and clear or zeroize any sensitive information included within the integrated circuit device. Electrode finger grids above and below the integrated circuit die detect physical attempts to penetrate the integrated circuit die. Critical circuit functions are segregated from non-critical functions. Power applied to the integrated circuit device is monitored and separated for critical and non-critical circuit functions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.