Fabrication of dense parallel solder bump connections
US5406701A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1993 |
| Grant date | Apr 18, 1995 |
| Priority date | — |
| Expiry date | Sep 13, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and product are disclosed in which multiple solder bumps on a first planar surface are guided into engagement with terminals on a second planar surface by means of holes formed (by a photolithographic process) in a dielectric layer, which has been added to the second surface to provide the holes (or sockets) through which the solder bumps (or plugs) extend. The perforated (hole-providing) layer may be formed of one of several materials. The preferred perforated layer material is a photo-definable polyimide, which is hardened by heating after the holes have been formed. Small solder bumps may be formed inside the holes on the second surface, in order to facilitate bonding between the solder bumps on the first surface and the terminals on the second surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.