CMOS process and circuit including zero threshold transistors
US5407849A · kind A · utility
19Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1992 |
| Grant date | Apr 18, 1995 |
| Priority date | — |
| Expiry date | Jun 23, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/07
Abstract
A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.