Computer graphics system with parallel processing using a switch structure
US5408606A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 1993 |
| Grant date | Apr 18, 1995 |
| Priority date | — |
| Expiry date | Jan 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Front end processors in a graphics architecture execute parallel scan conversion and shading to first process individually assigned primitive objects for providing update pixels. A crossbar accommodates data rearrangement whereby parallel pixel processors with associated memory capabilities (frame buffer banks) perform visibility and blending operations on predetermined sequences of update pixels to provide display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines or distributed over an area. Specific distribution criteria are disclosed for patterns. One form of pixel processor organization incorporates a distributed frame buffer with FIFO memory and control stacks. Display pixels are received by a multiplexer to supply a digital-analog connector with display data in raster sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.