Configurable multiport memory interface
US5408627A · kind A · utility
26Cited by
12References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1990 |
| Grant date | Apr 18, 1995 |
| Priority date | — |
| Expiry date | Jul 30, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention uses a logic control to determine which of a plurality of processors receives priority, and generates WAIT signals for the non-selected processor. Further, user configurable pins exist that allow the user to determine the priority that the attached processor will obtain when simultaneous chip selects are transmitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.