Solid state recorder with flexible width data bus utilizing lock mapping and error correction and detection circuits
US5408628A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 7, 1992 |
| Grant date | Apr 18, 1995 |
| Priority date | — |
| Expiry date | Jul 7, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid state data recorder employs a solid state memory to record data in the form of data words of variable length transmitted to the memory on a flexible width data bus. The memory is monitored to determine failed memory locations, and such locations are mapped out so as not to be used to store data. Bus lines are selected lines in accordance with mapped out memory locations in order to transfer the variable length data words to and from the memory. By employing the variable length data words and flexible width data bus, loss of useable recording space in the memory is very gradual, thus minimizing the amount of spare memory area required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.