System for flushing first and second caches upon detection of a write operation to write protected areas
US5408636A · kind A · utility
23Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1994 |
| Grant date | Apr 18, 1995 |
| Priority date | — |
| Expiry date | Jun 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system that flushes an internal cache in the microprocessor and an external cache to insure cache coherency. The computer system will flush the caches when a write command is directed to those specific portions that are write protected. The microprocessor is placed in a hold state before the flushing process is initiated. The cache memories are then cleared. Thus the microprocessor will not be able to read the incoherent information stored in the cache and yet data obtained during read operations can be cached for performance increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.