Thin film transistor and preparation thereof
US5410172A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1992 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Dec 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor is provided with a semiconductor layer disposed on an insulating layer region having a channel region and a plurality of main electrode regions having an impurity concentration higher than an impurity concentration of the channel region. A second insulating layer region is disposed on the semiconductor region layer, and a control electrode is disposed on the second insulating layer. An interface is defined between at least one of the main electrode regions and the channel regions through a thickness of the semiconductor layer becoming increasing remote from its side of the control electrode in the direction from the second insulating layer region toward the first insulating layer region. An original point is defined as a position of the interface immediately beneath the insulating layer region. When a layer thickness of the semiconductor region is defined as T.sub.SOI and a maximum distance of the semiconductor layer region in the direction normal to a layer thickness is defined as L.sub.UP a value, the ratio of L.sub.UP /T.sub.SOI is at least 0.35.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.