Decimation circuit and method for filtering quantized signals while providing a substantially uniform magnitude and a substantially linear phase response
US5410498A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1994 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Apr 5, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decimation circuit for filtering a stream of quantized electrical signals while providing a substantially uniform magnitude and a substantially linear phase response over a predetermined passband range F.sub.B is provided. The stream of quantized electrical signals arrives at a predetermined rate F.sub.M from an oversampling delta-sigma modulator. The decimation circuit includes a decimation filter for filtering the stream of quantized electrical signals to provide a filtered output signal at an output rate F.sub.S. The decimation filter has a frequency response defined by ##EQU1## wherein k is a positive integer, T is the sampling period of the decimation filter and R is a decimation ratio defined by R=F.sub.M /F.sub.S. A magnitude corrector is coupled to the decimation filter to receive the filtered output signal and to correct the magnitude of the received filtered signal at least over the predetermined range F.sub.B. The decimation ratio is selected such that output rate F.sub.S is sufficiently situated above bandpass range F.sub.B such that the magnitude corrector provides a desired substantially uniform magnitude and a substantially linear phase response over the passband r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.