Signal computing bus
US5410542A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1993 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Mar 1, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/6418
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A signal computing bus (SCbus) includes two bus structures: (a) a synchronous TDM data transport referred to as a data bus and (b) a serial message passing bus referred to as a message bus. The following three groups of functions are performed using the SCbus: (a) data transport over the data bus, (b) message passing over the message bus, and (c) data and message bus control. In a preferred embodiment, the data bus utilizes: 2 clocks, 1 frame pulse, 16 data busses, and 1 clock control (the clock control signal enables access to the bus and automatic switching from one clock master to another when an error is detected) and the message bus is fabricated using a master HDLC protocol with contention resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.