Test pattern fault equivalence
US5410548A · kind A · utility
12Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1992 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Oct 28, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for determining test pattern fault equivalence. The method comprises selecting a bridging fault (16) from a digital circuit, then determining a stuck-at fault (17) which guarantees detection of the bridging fault. Generation of a test vector (18) which detects the stuck-at fault. Simulating the test vector (19) to find all bridging faults that are detected by the test vector, and repeating the above steps until the desired percentage of detectable bridging faults are examined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.