Viterbi decoding apparatus
US5410555A · kind A · utility
9Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1992 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Nov 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/41
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Viterbi decoding apparatus capable of decoding convolutional codes of 30 Mbps or more in information quantity for such applications as high-definition television broadcasting. The apparatus comprises a path memory circuit and an ACS.SM normalizing circuit. The path memory circuit is made of path memory cells arranged in matrix fashion for shifting a path decoded word in units of a plurality of time slots in accordance with a transition diagram corresponding to that plurality of time slots and on the basis of path selection signals from the ACS.SM circuit that calculates data in units of that plurality of time slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.