Method and system for cache memory congruence class management in a data processing system
US5410663A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1992 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Oct 15, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for cache memory congruence class management in a data processing system. A selected address within a data processing system will typically have a single real address, but may have multiple virtual addresses within multiple virtual address spaces in a multi-tasking system, each virtual address space including a segment index, a page index and a byte index. A memory cache may be utilized to improve processor performance by hashing a portion of each virtual memory address to an address within a congruence class in the cache; however, when the cache contains a greater number of congruence classes than the number of different byte index addresses the virtual memory addresses of a single real memory address may hash to different congruence classes, reducing the ability of the processor to rapidly locate data within the cache. The method and system prevents this problem by first determining whether or not a virtual memory address exists within any virtual memory space in the system which corresponds to a selected address in real memory, in response to a request for a virtual memory address corresponding to that selected address. If such a virtual memory address alread…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.