RAM addressing apparatus with lower power consumption and less noise generation
US5410664A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1993 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Mar 31, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address converter that reduces the number of address bit changes between successive sequential addresses is provided to a RAM address bus for a sequentially accessed RAM. In the presently preferred embodiment, the address converter comprises a plurality of XOR gates for converting the access addresses into gray coded access addresses having at most one address bit change between successive access addresses. As a result, the power consumed and the noise generated over the address bus is reduced, thereby conserving power available and minimizing device package pins required by the digital system having the RAM and the RAM address bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.